The present invention relates, in general, to integrated circuits and, more particularly, to programmable integrated circuits.
Field Programmable Gate Array (FPGA) integrated circuits are comprised of an array of Configurable Logic Blocks (CLBs) dynamically interconnected through programmable switches. Each of the CLBs includes logic gates, clocked latches, pass-gate transistors, and feedback structures having interconnects that are also configured through programmable switches. The switches are programmed by data stored in configuration memory cells. Thus, the specific logic functions performed within the CLB as well as the interconnect between multiple CLBs are configured by specific data in the cells.
An electrical signal in an FPGA is typically transferred through multiple programmable switches prior to reaching its destination. The programmable switches are comprised of either N-channel and P-channel complementary transistors or N-channel pass-gate transistors controlled by the configuration memory cells. The configuration memory cells require considerable area for the active transistor devices of the cells and for the metal interconnects that route the serial data between cells. Additional area is required for the metal interconnecting each of the memory cells to the corresponding complementary transistors or pass-gate transistors that form the programmable switches.
The configuration memory cells lose stored data when power is removed from the FPGA. An external nonvolatile memory, such as an Electrical Erasable Programmable Read Only Memory (EEPROM), provides the configuration data that reprograms the internal cells after a power loss. The reprogramming process is relatively slow due to the use of an external nonvolatile memory for providing configuration data.
Accordingly, it would be advantageous to have programmable switches that occupy a small active area in an FPGA while maintaining a high current carrying capability. It would be of further advantage to have a method for programming the switches thereby allowing logic reprogramming during circuit operation. In addition, it is desirable to have switches capable of retaining switch information during power interruption thereby eliminating the need for reprogramming the FPGA after a power loss. Another desired advantage would eliminate the external nonvolatile memory whose data can be probed during reprogramming for determining the configuration of the FPGA.